8. HIGH SPEED COUNTER MODULE CONNECTIONS B-61813E/03
2) CMPA, CMPB, and CMPC (comparison output signals A, B,
and C, only in mode A)
The CMPA, CMPB, and CMPC signals are output signals
resulting from the comparison between the comparison
registers A, B, and C and the counter data, respectively. The
output levels of CMPA, CMPB, and CMPC are determined
by the comparison mode signals CMA, CMB, and CMC.
When CMA, CMB, and CMC are 0, and the counter data is
larger than the values in comparison registers A, B, and C,
CMPA, CMPB, and CMPC are set to 1.
When CMA, CMB, and CMC are 1, and the counter data is
equal to or less than the values in comparison registers A, B,
and C, CMPA, CMPB, and CMPC are set to 1.
3) OUT0 to OUT 7 (comparison output signal 0 to comparison
output signal 7, only in mode B)
OUT0 - OUT7 correspond to bit 0 to bit 7 in the comparison
result output of a single byte.
4) MH (marker hold signal)
The marker hold signal MH is set to 1 at the rising edge of
the marker signal whenthe marker enable signal is 1. The
marker hold signal is reset when MHR=1 or MS=0. (In mode
B, the marker hold signal MH is reset only when MS=0.)
5) ME (marker enable signal)
The marker enable signal ME enables the marker signal as
ME=1: Marker signal enabled
ME=0: Marker signal disabled
6) CSP (count stop signal)
The counter stops counting when the contact for the external
input signal CSP is closed.
7) ALM (alarm signal)
The alarm signal ALM is set to 1 if the signal line for the
count pulse or the marker signal is disconnected or short-
ALM is also set to 1 when the watch dog alarm is activated.
(2) PMC outputs (outputs from PMC)
1) SELECT (selection signal)
The SELECT signal selects the register in which data will be
set. That is, the signal specifies the register for presetting
data. The SELECT signal should be set when or before the
PRS signal is reversed.