
9.CONNECTION B-65282EN/05
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Phase A/B signal
Width of phase A/B signal
PA,*PA,PB,*PB
Tpwh Tpwl
Phase difference between phase A and phase B
PA
Tpw0
CCW directionCW direction
Tpw1 Tpw2 Tpw3
PB
*PA and *PB represent the negative logic signals of PA and PB,
respectively.
Symbol Specification Remark
Tpwh, Tpwl Min 636ns
Tpw0,1,2,3 Min 636ns
Including a maximum of driver rising/falling
delay time skew (30 ns)
This specification does not include the effect of the cable capacity
and the skew due to delay on the receiver side.
CAUTION
As shown in state A below, a waveform may be
distorted at the edge of phase A or B.
In addition, the edge may be encountered too late
or too early as shown in state B or C. Even in these
states, the minimum time is defined according to
the specifications described on the previous page,
such as the pulse width and the difference between
phase A and phase B.
PA
PB
A
C
B