
4.LADDER LANGUAGE B-63983EN/02
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4.1.1 Details of the Basic Instructions
Table 4.1.1 lists the types of the basic instructions and explains the
processing they perform.
The difference between the two types of formats shown under
Instruction is described below.
Mnemonic format:
The instructions are displayed in this format when you edit or
print a ladder program that has been converted to the mnemonic
format with FANUC LADDER-III, by using a commercially
available text editor.
Mnemonic format (abbreviated):
These are the abbreviated forms of instructions that you can use
when editing a ladder program that has been converted to the
mnemonic format with FANUC LADDER-III, by using a
commercially available text editor. If you input a file in this
abbreviated format and convert it again to the ladder diagram
format with FANUC LADDER-III, the code in the file can still
be recognized as being written in the valid mnemonic format.
Detailed explanations of the individual basic instructions follow.
Table 4.1.1
Instruction
No.
Mnemonic
format
Mnemonic
format
(abbreviated)
Processing
1 RD R Reads the status of the specified signal and sets it in the ST0 bit.
2 RD.NOT RN Reads and reverses the logical status of the specified signal and sets it in the ST0
bit.
3 WRT W Outputs the logical operation result (the status of the ST0 bit) to the specified
address.
4 WRT.NOT WN Reverses and outputs the logical operation result (the status of the ST0 bit) to the
specified address.
5 AND A Produces a logical product.
6 AND.NOT AN Reverses the logical status of the specified signal and produces a logical product.
7 OR O Produces a logical sum.
8 OR.NOT ON Reverses the logical status of the specified signal and produces a logical sum.
9 RD.STK RS Shifts the register content one bit to the left and sets the status of the signal at the
specified address in the ST0 bit.
10 RD.NOT.STK RNS Shifts the register content one bit to the left, reads and reverses the logical status
of the signal at the specified address, and sets it in the ST0 bit.
11 AND.STK AS Sets the logical product of the ST0 and ST1 bits in the ST1 bit and shifts the
register content one bit to the right.
12 OR.STK OS Sets the logical sum of the ST0 and ST1 bits in the ST1 bit and shifts the register
content one bit to the right.
13 SET SET Finds the logical sum of the ST0 bit and the status of the signal at the specified
address and outputs it to the specified address.
14 RST RST Finds the logical product of the reversed status of the ST0 bit and the status of the
signal at the specified address and outputs it to the specified address.