
B–62075E/04
5. TROUBLESHOOTING
290
<Second override>
#7
*AFV7G013
#6
*AFV6
#5
*AFV5
#4
*AFV4
#3
*AFV3
#2
*AFV2
#1
*AFV1
#0
*AFV0
(M/T series,
TT series
HEAD #1)
#7
*AFV7G061
#6
*AFV6
#5
*AFV5
#4
*AFV4
#3
*AFV3
#2
*AFV2
#1
*AFV1
#0
*AFV0
(TT series
HEAD #2)
c. The manual feedrate override is 0% (only for dry run).
When the dry run signal is turned on during cycle operation, the
following override is enabled for the dry run feedrate. Check the state
of the signals by using the PMC diagnostic function (PMC DGN).
#7
*JV15G014
#6
*JV14
#5
*JV13
#4
*JV12
#3
*JV11
#2
*JV10
#1
*JV9
#0
*JV8
(M/T series)
#7
*JV7G015
#6
+JV6
#5
*JV5
#4
*JV4
#3
*JV3
#2
*JV2
#1
*JV1
#0
*JV0
(M/T series)
#7
*JV15G104
#6
*JV14
#5
*JV13
#4
*JV12
#3
*JV11
#2
*JV10
#1
*JV9
#0
*JV8
(TT series)
#7
*JV7G105
#6
+JV6
#5
*JV5
#4
*JV4
#3
*JV3
#2
*JV2
#1
*JV1
#0
*JV0
(TT series)
When the override is 0%, the bits of the above addresses are set to
all 1 or all 0.
d. An interlock/start lock signal is being input.
Check the signal by using the PMC diagnostic function (PMC DGN).
(i) The interlock signal (*IT) is being input.
#7
G000
#6 #5 #4 #3 #2 #1 #0
*IT
(M/T series)
#7
G096
#6 #5 #4 #3 #2 #1 #0
*IT
(TT series)
0 in the *IT bit indicates that the interlock signal is being
input.
(ii) An axis interlock signal (*ITn), servo off signal (*SVFn), or
controlled axis detachment signal (DTCHn) is being input.
#7
DTCH1G064
#6
*SVF1
#5 #4
*IT1
#3 #2 #1 #0
(M/T series
first axis)
#7
DTCH1G128
#6
*SVF1
#5 #4
*IT1
#3 #2 #1 #0
(TT series
first axis)
The address for the nth axis is as follows:
M/T series: 64 + (n – 1)*4
TT series: 128 + (n – 1)*4
0 in the *ITn or *SVFn bit or 1 in the DTCHn bit indicates that
the corresponding signal is being input.